1. Field of the Invention
The invention relates to a phase locked loop, and more particularly to a phase locked loop, which has low steady state phase errors by utilizing a delay unit to delay a phase of an input signal or a reference clock so as to compensate for the circuit property, and a calibration circuit for the same.
2. Description of the Related Art
FIG. 1 shows a block diagram of a conventional phase locked loop (hereinafter is called PLL). The PLL is used to provide a phase locked clock PLCK in sync with the phase of the input signal IN. For example, when an optical drive is reading the data on an optical disc medium, the PLL is used to lock the phase and frequency of the EFM (Eight-to-Fourteen Modulation) signal and output a phase locked clock PLCK as a sampling clock or other control reference clocks for the EFM signal. Referring to FIG. 1, the conventional PLL 10 includes a phase detector 11, a charge pump 12, a loop filter 13, a voltage control oscillator (VCO) 14, and a frequency divider 15. The phase detector 11 detects the phase difference between the input signal IN and the phase locked clock PLCK, and outputs charge control signals UP and DOWN to control the charge pump 12 according to the phase difference. For example, when the phase of the phase locked clock PLCK leads that of the input signal IN, the pulse width of the charge control signal UP is smaller than the pulse width of the charge control signal DOWN so that the charge pump 12 generates a negative control current Icp. Then, the loop filter 13 reduces the control voltage Cv according to the negative control current Icp so as to control the VCO 14 to lower the frequency of the phase locked clock PLCK. On the contrary, when the phase of the phase locked clock PLCK lags behind that of the input signal IN, the pulse width of the charge control signal UP is greater than the pulse width of the charge control pulse DOWN so that the charge pump 12 generates a positive control current Icp. The loop filter 13 increases the control voltage Cv according to the negative control current Icp so as to control the VCO 14 to rise the frequency of the phase locked clock PLCK.
In the conventional PLL, however, the current mismatch in the charge pump or the logic delay mismatch between the up and down paths may cause phase errors between the input signal IN and phase locked clock PLCK even though the input signal IN and clock PLCK have been already locked on a steady state. Therefore, it is important to provide a PLL with low steady state phase errors.